Semiconductor package is a resin-encapsulated structure incorporated with at least one integrated circuit component such as semiconductor chip that is enclosed by an encapsulating resin for protection. A chip carrier (e.g. substrate, lead frame, etc.) is usually employed to mount and electrically connect the semiconductor chip. A conventional electrical connection is achieved by using a plurality of conductive bonding wires (such as gold wires) to interconnect an active surface of the chip and the chip carrier, and the bonding wires are also encapsulated by the encapsulating resin. However, the bonding wires possess predetermined length and loop height, such that they occupy a certain extent of surface area on the chip carrier; further, an encapsulation body formed by the encapsulating resin is required having a height larger than the loop height to completely enclose the bonding wires and prevent the bonding wires from exposure that may damage the electrical performance of the bonding wires, such that the package size is hardly reduced. Accordingly, a flip-chip package is developed, characterized in pre-forming a plurality of bumps on the active surface of the chip for electrical connection, and allowing the chip to be mounted on and electrically connected to the chip carrier by the bumps. Unlike the bonding wires, the use of bumps, not having the concern of length and loop height, can effectively reduce the package size.
During fabrication of a flip chip, normally when a wafer comprising a plurality of chips is fabricated, a bumping process is performed using conventional screen printing technology to deposit tin-lead alloy at bond pads formed on active surfaces of the chips, and the tin-lead alloy is reflowed to form bumps. Then, the chips of the wafer are required subject to electrical tests to examine the quality and functionality of the chips, so as to figure out inferior chips having defective quality and functions. After the wafer undergoes a singulation process to separate apart the chips, the inferior chips are discarded, only allowing the chips passing the tests to be subject to subsequent fabrication processes.
The above electrical tests can be performed before and after forming the bumps on the wafer; the former is shown in FIGS. 6A and 6B. In FIG. 6A, test probes 2 directly contact bond pads 13 formed on the wafer 1 to perform the tests. In FIG. 6B, after the tests, a UBM (under bump metallurgy) structure 15 is formed respectively on the bond pads 13 to allow a bump 14 to be formed on each UBM structure 15. However, this test method undesirably causes a notch on or damage to the bond pads 13 (FIG. 6A) or the UBM structure 15 by direct contact of the test probes 2. When the notched UBM structure 15 is connected with the bump 14, a void trapped with air would form at the notch and easily leads to popcorn effect thereby degrading the reliability of fabricated products.
Therefore, the more commonly used method is to perform the tests after the bumping process; as shown in FIG. 6C, the test probes 2 directly contact the bumps 14 on the wafer to carry out the electrical tests on the chips 10. However, this method easily damages the bumps 14 and thus affects yield of subsequent chip packaging.
Moreover, U.S. Pat. No. 6,429,532 discloses a special arrangement of bond pads including a plurality of test bond pads that are electrically connected to bond pads formed with bumps, such that test probes contact the test bond pads to perform tests. However, this bond-pad arrangement requires additional surface area on the wafer for disposing the test bond pads, thereby not favorable for size miniaturization.
In addition, U.S. Pat. No. 5,661,042 discloses the use of an anisotropic conductive film (ACF) as a conductive medium between the wafer and the test probes, to allow an electrical current to flow through the ACF for performing the wafer tests. However, this technology is defective that the ACF has high conductive resistance and is only suitable for mediating the current but not for test performance; further, the ACF has short contact lifetime (about 50 times) and cannot be used repeatedly, and the ACF is expensively fabricated, thereby undesirably increasing the fabrication costs.
Therefore, the problem to be solved herein is to provide a wafer test method carried out before forming bumps on the wafer, which would not damage bond pads on the wafer and not increase fabrication costs.